1. Field of the Invention
This invention concerns a chemical mechanical polishing (CMP) composition including a compound capable of etching tungsten and at least one inhibitor of tungsten etching. The polishing composition is useful alone or in combination with other chemicals and abrasives for polishing metal layers and thin-films associated with semiconductor manufacturing where one of the layers or films is comprised of tungsten.
2. Description of the Related Art
Integrated circuits are made up of millions of active devices formed in or on a silicon substrate. The active devices, which are initially isolated from one another, are united to form functional circuits and components. The devices are interconnected through the use of well-known multilevel interconnections. Interconnection structures normally have a first layer of metallization, an interconnection layer, a second level of metallization, and sometimes a third and subsequent levels of metallization. Interlevel dielectrics such as doped and undoped silicon dioxide (SiO.sub.2), are used to electrically isolate the different levels of metallization in a silicon substrate or well. The electrical connections between different interconnection levels are made through the use of metallized vias and in particular tungsten vias. U.S. Pat. No. 4,789,648, which is incorporated herein by reference, describes a method for preparing multiple metallized layers and metallized vias in insulator films. In a similar manner, metal contacts are used to form electrical connections between interconnection levels and devices formed in a well. The metal vias and contacts are generally filled with tungsten and generally employ an adhesion layer such as titanium nitride (TiN) and/or titanium to adhere a metal layer such as a tungsten metal layer to SiO.sub.2.
In one semiconductor manufacturing process, metallized vias or contacts are formed by a blanket tungsten deposition followed by a chemical mechanical polish (CMP) step. In a typical process, via holes are etched through an interlevel dielectric (ILD) to interconnection lines or to a semiconductor substrate. Next, a thin adhesion layer such as titanium nitride and/or titanium is generally formed over the ILD and is directed into the etched via hole. Then, a tungsten film is blanket deposited over the adhesion layer and into the via. The deposition is continued until the via hole is filled with tungsten. Finally, the excess tungsten is removed by chemical mechanical polishing (CMP) to form metal vias. Processes for manufacturing and/or CMP of ILD's are disclosed in U.S. Pat. Nos. 4,671,851, 4,910,155 and 4,944,836.
In a typical chemical mechanical polishing process, the substrate is placed in direct contact with a rotating polishing pad. A carrier applies pressure against the backside of the substrate. During the polishing process, the pad and table are rotated while a downward force is maintained against the substrate back. An abrasive and chemically reactive solution, commonly referred to as a "slurry" is deposited onto the pad during polishing. The slurry initiates the polishing process by chemically reacting with the film being polished. The polishing process is facilitated by the rotational movement of the pad relative to the substrate as slurry is provided to the wafer/pad interface. Polishing is continued in this manner until the desired film on the insulator is removed.
The slurry composition is an important factor in the CMP step. Depending on the choice of the oxidizing agent, the abrasive, and other useful additives, the polishing slurry can be tailored to provide effective polishing of metal layers at desired polishing rates while minimizing surface imperfections, defects, corrosion, and erosion of oxide in areas with tungsten vias. Furthermore, the polishing slurry may be used to provide controlled polishing selectivities to other thin-film materials used in current integrated circuit technology such as titanium, titanium nitride and the like.
Typically CMP polishing slurries contain an abrasive material, such as silica or alumina, suspended in an oxidizing, aqueous medium. For example, U.S. Pat. No. 5,244,523 to Yu et al. reports a slurry containing alumina, hydrogen peroxide, and either potassium or ammonium hydroxide that is useful in removing tungsten at predictable rates with little removal of the underlying insulating layer. U.S. Pat. No. 5,209,816 to Yu et al. discloses a slurry comprising perchloric acid, hydrogen peroxide and a solid abrasive material in an aqueous medium. U.S. Pat. No. 5,340,370 to Cadien and Feller discloses a tungsten polishing slurry comprising approximately 0.1M potassium ferricyanide, approximately 5 weight percent silica and potassium acetate. Acetic acid is added to buffer the pH at approximately 3.5.
Most of the currently available CMP slurries contain large concentrations of dissolved, ionic metallic components. As a result, the polished substrates can become contaminated by the adsorption of charged species into the interlayers. These species can migrate and change the electrical properties of the devices at gates and contacts and change the dielectric properties of the SiO.sub.2 layers. These changes may reduce the reliability of the integrated circuits with time. Therefore, it is desirable to expose the wafer only to high purity chemicals with very low concentrations of mobile metallic ions.
CMP compositions are increasingly being formulated with chemical ingredients that are capable of etching tungsten in an effort to improve the rate at which tungsten vias are polished. However, in many cases the resulting CMP slurry compositions etch tungsten in a manner that solubilizes the tungsten instead of converting the surface to a soft oxidized film with improved tungsten abradeability. Due to these chemical compositions, recessing of the tungsten plug due to undesireable tungsten etching occurs. Recessed tungsten vias, where the surface of the tungsten is below that of the surrounding insulator surface, are a problem because they can cause electrical contact problems to other parts of the device. In addition, problems due to tungsten recess may be caused by the fact that the resulting nonplanarity may complicate the deposition of metal layers on subsequent levels of the device.
Tungsten etching can also cause undesireable "keyholing" of tungsten vias. Keyholing is a phenomenon whereby a hole is etched into the center of a tungsten via and, thereafter, the hole migrates towards the sides of the via. Keyholing causes the same contact and filling problems as recessing.
A new CMP composition is needed that both polishes tungsten at high rates and that does not cause undesirable tungsten plug recessing.